Rafael A. Arce Nazario

Office: CN C1
Extension: 7429, 88361
Website: http://ccom.uprrp.edu/~rarce/
Email: rafael.arce@upr.edu

  • Ph.D. in Computer and Information Sciences and Engineering. Universidad de Puerto Rico, Mayagüez (2007)
  • M.Sc. (Hons.) in Electrical Engineering. University of Winsconsin (1993)
  • B.Sc. (Hons.) in Computer Engineering. Universidad de Puerto Rico, Mayagüez (1992)

Research Areas

Mapping of algorithms to dedicated hardware architectures, high-level synthesis in electronic design automation, analysis/design of algorithms for bioinformatics, hardware/software codesign for custom computing machines.


Publications

    Articles

      Published
      • Rafael A. Arce Nazario, Francis Castro, Oscar González, Luis Medina, Ivelisse Rubio Canabal (2017). New families of balanced symmetric functions and a generalization of Cusick, Li and Stanica's conjecture. To be published in Designs, Codes and Cryptography
      • Jose R Ortiz Ubarri, Rafael A. Arce Nazario, Ivelisse Rubio Canabal, Cynthia Lucena (2016). EIP: Engaging Laboratory Experiences for the Introduction to Programming Course. To be published in Envisioning the future of undergraduate STEM education: Research and practice
      • R. Arce-Nazario, F. Castro, J. Cordova, K. Hicks, G. Mullen, I. Rubio (2014). Some Computational Results Concerning the Spectrum of Sets of Latin Squares. Quasigroups and related systems, 22, 159-164
      • Rafael A. Arce Nazario, Jose R Ortiz Ubarri (2011). Enumeration of Costas Arrays in FPGAs and GPUs. 2011 International Conference on ReConFigurable Computing and FPGAs
        http://www.reconfig.org/
      • Edusmildo Orozco Salcedo, Rafael A. Arce Nazario, Peter M. Musial, Cynthia Lucena (2011). Asserting Parallel Computational Thinking into an undergraduate computer science curriculum. Computer Science Education: Innovation and Technology CSEIT 2011, 0
        http://cseducation.org/
      • Rafael A. Arce Nazario, Edusmildo Orozco Salcedo, Dorothy Bollman (2010). Reconfigurable hardware implementation of a multivariate polynomial interpolation algorithm. International Journal of Reconfigurable Computing, 2010, 0, --
        http://dl.acm.org/citation.cfm?id=1972685
      • R. Arce-Nazario,E. Orozco, D. Bollman, (2009). A systolic array based architecture for implementing multivariate polynomial interpolation tasks. 2009 International Conference on ReConFigurable Computing and FPGAs
      • R. Arce and M. Jiménez (2008). Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms. 2008 International Conference on ReConFigurable Computing and FPGAs
      • R. Arce, M. Jimenez, D. Rodriguez (2008). Mapping of discrete cosine transforms onto distributed hardware architectures. Journal of Signal Processing Systems
        ISSN:1939-8018
      • R. Arce, M. Jimenez, D. Rodriguez (2007). Partitioning Exploration for Automated Mapping of Discrete Cosine Transforms onto Distributed Hardware Architectures. 50th IEEE Midwest Symposium on Circuits and Systems
      • R. Arce, M. Jimenez, D. Rodriguez (2007). Algorithmic-level Exploration of Discrete Signal Transforms for Partitioning to Distributed Hardware Architectures. IET Computers & Digital Techniques, 557 - 564
      • R. Arce, M. Jimenez, D. Rodriguez (2006). Algorithmic-level Exploration of Discrete Signal Transforms for Partitioning to Distributed Hardware Architectures. IET Computers & Digital Techniques
      • R. Arce, M. Jimenez, D. Rodriguez (2006). High-level Partitioning of Discrete Signal Transforms for Partitioning to Distributed Hardware Architectures. 16th IEEE International Conference on Field Programmable Logic and Applications
      • R. Arce, M. Jimenez, D. Rodriguez (2006). Functionally-aware Partitioning of Discrete Signal Transforms for Distributed Hardware Architectures. 49th IEEE Midwest Symposium on Circuits and Systems
      • R. Arce, M. Jimenez, D. Rodriguez (2006). Effects of High-Level Discrete Signal Transforms Formulations on Partitioning for Distributed Hardware Architectures. IEEE on Symposium Field-Programmable Custom Computing Machines
      • R. Arce, M. Jimenez, D. Rodriguez (2005). An Assessment of High-Level Partitioning Techniques for Implementing Discrete Signal Transforms on Distributed Hardware Architectures. 48th IEEE Midwest Symposium on Circuits and Systems
      • B. Lembach, R. Arce, D. Eisenmenger, C. Wood (2005). A diagnostic method for detecting and assessing th eimpact of physical design optimizations on routing. ACM International Symposium on Physical Design
      • R. Arce, M. Jimenez (2003). Integer Pair Representation for Multiple Output Logic. 47th IEEE Midwest Symposium on Circuits and Systems
      • R. Arce, M. Jimenez (2003). Integer Pair Representation for Multiple Output Logic. Proceedings of the Computing Research Conference
      • R. Arce (1994). Multisensory Interface to Allow Blind User Access to Graphics. Proceedings of RESNA 1994 Anunual Conference
      Submitted
      • Francis Castro, Domingo Gómez, Oscar Moreno, Jose R Ortiz Ubarri, Ivelisse Rubio Canabal, Andrew Tirkel, Rafael A. Arce Nazario. Linear Complexity Analysis of Multidimensional Periodic Arrays
      • R. Arce, F. N. Castro, R. Figueroa. On the Number of Solutions of $\displaystyle{\sum_{i=1}^k \frac{1}{x_i}=1} $ in Distinct Odd Natural Numbers


Professional Activities

    Talks

    • On the Number of Solutions of $\Sigma_{i=1}^{k} ]frac{1}{x_i} = 1$ in Distinct Odd Natural Numbers, SIDIM (2010)
    • The Reconfigurable Computing Laboratory at the UPR–RP, SIDIM (2010)
    • A systolic array based architecture for implementing multivariate polynomial interpolation tasks, SIDIM (2010)
    • Partitioning of Discrete Signal Transforms onto Distributed Hardware Architectures , Universidad Politécnica de Puerto Rico (2009)
    • New computational Solutions for Latin Square n=6 Orthogonality, UPR-RP (2009)
    • High-Level Partitioning of DSP Algorithms for Multi-FPGA Systems - A First Approach, Proceedings of the Computing Research Conference (2004)


Grants

    Submitted

    • Collaborative Project: A High-level Modeling Framework for Partitioning Signal Processing Systems onto Multicore Architectures , MCDA - NSF
      Role: PI (Principal Investigator)
      Funds: $900,000

    Current

    • Scholarship fund for excellence in Computer Science and Mathematics, NSF
      Role: PI (Principal Investigator)
      Start date: September 1, 2014 | End date: August 1, 2017
      Funds: $630,217
    • Development of engaging and readily transferable laboratory experiences for the introductory programming course, NSF
      Role: Co-PI (Co-Principal Investigator)
      Start date: September 15, 2013 | End date: September 14, 2013
      Funds: $193,997
    • CC-NIE Networking Infrastructure: Perimeter Network to Expedite the Transmission of Science Project (PR NETS), NSF
      Role: Co-PI (Co-Principal Investigator)
      Start date: October 1, 2013 | End date: September 30, 2015
      Funds: $499,667

    Completed

    • Asserting Parallel Computational Thinking into Undergraduate 4-year Computer Science Curriculum, CPATH-NSF
      Role: PI (Principal Investigator)
      Start date: October 1, 2009 | End date: September 30, 2012
      Funds: $300,000
    • Acquisition of Equipment for the Establishment of a Reconfigurable Computing Center at the University of Puerto Rico, NSF-MRI
      Role: PI (Principal Investigator)
      Start date: September 30, 2009 | End date: September 30, 2012
      Funds: $186,000